Scheda insegnamento (lingua inglese)

Scheda insegnamento (lingua inglese)

Stampato il 01.06.2024 ore 16:24

Title

Reti logiche
Introduction to Logic Design
mutua da Reti logiche

Degree

Corso di Laurea Specialistica in Ingegneria Gestionale
Second Level Degree in Management Engineering
Corso di Laurea in Ingegneria Elettronica

Year

Teaching Period

Credits

Teacher: Tiziano Villa

Academic year: 2005/2006

Objectives:

The class introduces the main techniques for the analysis and synthesis of combinational and sequential logic networks.

Requirements:

Acquired skills:

Understand the terminology and mathematical theory to model digital logic.
Analyze the behavior of combinational and sequential logic networks.
Derive from informal specifications the truth table of a combinational function, minimize and realize it with two-level logic.
Derive from informal specifications the state diagram of a finite state machine, minimize, encode and realize it with combinational logic and memory elements.

Lectures and exercises		hours
Topics	Specific contents
Introduction to modern logic design	.	4
Boolean algebra		6
Two-level and multi-level minimization		6
Complex combinational networks		2
Programmable logic and memories		2
Arithmetic circuits		4
Delay in combinational circuits		2
Sequential networks		6
Complex sequential networks		2
Delay in sequential circuits		2
Finite state machines		3
Design of sequential systems		4
Total hours for lectures and exercises		43
for exercises only
Further educational activities		hours
Labs
Tutorials / Seminars
Workshops
Guided tours
Description of final project		1
Total hours for further educational activities		1
Total hours		44

Type of exam: Written

References:

R. H. Katz, ``Contemporary Logic Design'', Addison Wesley Publishing Company, Reading, MA, 1993.
F. Luccio e L. Pagli, ``Reti logiche e calcolatore'', Bollati Boringheri, Torino, 1991.

Additional material or information on line http:// www.parades.rm.cnr.it/~villa/didattica/reti_log/rl_aut02.html

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