| Lectures and exercises |
hours |
| Topics |
Specific contents |
|
| Optimization of finite state machines |
Minimization of incompletely specified finite state machines.
State assignment.
Choice of flip-flops.
Finite state machine partitioning.
|
6
|
| Finite state machine implementation |
Finite state machine design with programmable logic (ROM and PLA),
FSM design with counters, FSM design with more sophisticated programmable
devices (PLD, Altera and Xilinx).
|
4
|
| Computer organization |
Central processing unit (control + datapath).
Block diagram and register transfer notation.
Interface to memory.
Input/output.
|
4
|
| Busing strategies |
Point-to-point connections, single bus, multiple buses. |
2
|
| Finite state machines for simple CPUs |
Deriving the state diagram and data path.
Register transfer operations and datapath control.
|
6
|
| Controller implementation |
Random logic (single Moore machine and synchronous Mealy machine).
Decomposition as a network of FSMs.
Jump counters.
Branch sequencers.
Horizontal and vertical microprogramming.
|
6
|
| Putting it all together: design of a simple microprocessor |
|
6
|
| Asynchronous circuits |
|
4
|
| Iterative circuits |
|
2
|
| Delay analysis |
|
2
|
| Total hours for lectures and exercises |
42 |
| for exercises only |
|
|
Further educational activities
|
hours
|
| Labs |
8 |
| Tutorials / Seminars |
|
| Workshops |
|
| Guided tours |
|
| |
|
| Total hours for further educational activities |
8 |
| Total hours |
50
|