Scheda insegnamento (lingua inglese)

Scheda insegnamento (lingua inglese)

Stampato il 02.06.2024 ore 14:11

Title

Reti logiche
Introduction to Logic Design
mutua da Metodologia della sintesi logica

Degree

Corso di Laurea in Ingegneria Elettronica
First Level Degree in Electrical Engineering
Corso di Laurea in Ingegneria Elettronica

Year

Teaching Period

Credits

Teacher: Mirko Loghi

Academic year: 2008/2009

Objectives:

The class introduces the main techniques for the analysis and synthesis of combinational and sequential logic networks.

Requirements:

Acquired skills:

Understand the terminology and mathematical theory to model digital logic.
Analyze the behavior of combinational and sequential logic networks.
Derive from informal specifications the truth table of a combinational function, minimize and realize it with two-level logic.
Derive from informal specifications the state diagram of a finite state machine, minimize, encode and realize it with combinational logic and memory elements.

Lectures and exercises		hours
Topics	Specific contents
Introduction to modern logic design		4
Boolean algebra		6
Two-level and multi-level minimization		6
Complex combinational networks		2
Programmable logic and memories		2
Arithmetic circuits		4
Delay in combinational circuits		2
Sequential networks		6
Complex sequential networks		2
Delay in sequential circuits		2
Finite state machines		3
Design of sequential systems		4
Total hours for lectures and exercises		43
for exercises only
Further educational activities		hours
Labs
Tutorials / Seminars
Workshops
Guided tours

Total hours for further educational activities		0
Total hours		43

Type of exam: Written

References:

R. H. Katz, "Contemporary Logic Design", Addison Wesley Publishing Company, Reading, MA, 1993.
Fummi, Sami, Silvano, "Progettazione digitale"

- Documento generato con SOFIA -